-- EMPTY PRR PARTIAL RECONFIGURABLE
-- PRAGMA standard control signal mapping:
-- clk								=> clk
-- reset								=> reset
-- PAY ATTENTION:					RESET IS ACTIVE LOW
-- control_in	(0) 				=> UNUSED
--					(7 downto 4) 	=> UNUSED
--					(3 downto 1) 	=> UNUSED
--
--	control_out	(3 downto 0)	<= UNUSED
-- 
-- PCM_data_in_right				<= PCM_data_in_right
-- PCM_data_in_left				<= PCM_data_in_left
-- PCM_data_out_right			<= PCM_data_out_right
-- PCM_data_out_left				<= PCM_data_out_left

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PRM_time_1 is
  port(
    clk				: in std_logic;
	 clk_48k			: in std_logic;
    reset			: in std_logic;
	 
	 control_in		: in std_logic_vector(7 downto 0);
	 control_out	: out std_logic_vector(3 downto 0);
	 
    PCM_data_in_right	: in std_logic_vector(15 downto 0);
	 PCM_data_in_left		: in std_logic_vector(15 downto 0);
    PCM_data_out_right	: out std_logic_vector(15 downto 0);
	 PCM_data_out_left	: out std_logic_vector(15 downto 0)
    );
end entity PRM_time_1;

architecture Behavioral of PRM_time_1 is

begin
	
	process (clk_48k, reset)
	begin
		if reset = '0' then
			PCM_data_out_right <= (others => '0');
			PCM_data_out_left <= (others => '0');
		elsif clk'event and clk = '1' then
			PCM_data_out_right <= PCM_data_in_right;
			PCM_data_out_left <= PCM_data_in_left;
		end if;
	end process;
	
	control_out	<= control_in(7 downto 4);

end Behavioral;

